cpldfit:  version G.31a                             Xilinx Inc.
                                  Fitter Report
Design Name: dlabdio5                            Date:  8-16-2004, 11:03AM
Device Used: XCR3128XL-7-TQ144
Fitting Status: Successful

****************************  Resource Summary  ****************************

Macrocells     Product Terms    Registers      Pins           Function Block 
Used           Used             Used           Used           Inputs Used    
89 /128 ( 70%) 198 /448  ( 44%) 50 /128 ( 39%) 96 /104 ( 92%) 201/320 ( 63%)

PIN RESOURCES:

Signal Type    Required     Mapped  |  Pin Type            Used   Remaining 
------------------------------------|---------------------------------------
Input         :   35          35    |  I/O              :    94        6
Output        :   43          43    |  GCK/IO           :     2        2
Bidirectional :   16          16    |  
GCK           :    2           2    |  
                 ----        ----
        Total      96          96 

MACROCELL RESOURCES:

Total Macrocells Available                   128
Registered Macrocells                         50
Non-registered Macrocell driving I/O          29

GLOBAL RESOURCES:

Signal 'clk' mapped onto global clock net GCK1.
Signal 'we' mapped onto global clock net GCK3.
Universal Control Terms (Used/Total)                      : 1/4

BLOCK RESOURCES:

Total Function Block Local Control Terms (Used/Total)     : 1/64
Total Foldback NANDs (Used/Total)                         : 0/64

End of Resource Summary
*************** Summary of Required Resources ******************

** LOGIC **
Signal              Total Signals Loc     Slew Pin  Pin       Pin     Reg Init
Name                Pt    Used            Rate #    Type      Use     State
N_PZ_229            2       6     FB1_11       97   I/O       I       
N_PZ_230            2       7     FB2_9             (b)       (b)     
N_PZ_232            2       7     FB2_8             (b)       (b)     
N_PZ_258            4       14    FB1_3        102  I/O       I       
N_PZ_264            4       10    FB1_4        101  I/O       I       
N_PZ_267            4       14    FB1_1        106  I/O       (b)     
N_PZ_283            1       2     FB2_10            (b)       (b)     
N_PZ_302            2       7     FB2_1        107  I/O       I       
N_PZ_335            1       2     FB3_2        89   TCK/I/O   (b)     
cntDig<0>           0       0     FB1_7        98   I/O       I       RESET
cntDig<1>           1       1     FB1_6        99   I/O       I       RESET
db<0>               6       13    FB3_16  SLOW 77   I/O       I/O     RESET
db<1>               6       13    FB3_14  SLOW 79   I/O       I/O     RESET
db<2>               6       13    FB3_12  SLOW 81   I/O       I/O     RESET
db<3>               6       13    FB3_7   SLOW 83   I/O       I/O     RESET
db<4>               6       13    FB3_5   SLOW 86   I/O       I/O     RESET
db<5>               6       13    FB3_3   SLOW 88   I/O       I/O     RESET
db<6>               6       13    FB3_1   SLOW 90   I/O       I/O     RESET
db<7>               6       13    FB1_15  SLOW 92   I/O       I/O     RESET
dig<0>              4       6     FB1_5        100  I/O       I       
encBtn<0>           5       9     FB2_2   SLOW 109  I/O       O       
encBtn<1>           5       10    FB2_3   SLOW 110  I/O       O       
encBtn<2>           5       10    FB2_4   SLOW 111  I/O       O       
encBtn<3>           1       8     FB2_5   SLOW 112  I/O       O       
kclk                1       1     FB2_15  SLOW 120  I/O       O       
kdat                1       1     FB2_16  SLOW 121  I/O       O       
lcden               3       8     FB5_2   SLOW 143  I/O       O       
lcdrs               1       1     FB6_1   SLOW 2    I/O       O       
lcdrw               1       1     FB5_1   SLOW 1    I/O       O       
regBtn<0>           0       0     FB4_12       69   I/O       I       RESET
regBtn<1>           0       0     FB4_5        65   I/O       I       RESET
regBtn<2>           0       0     FB4_6        66   I/O       I       RESET
regBtn<3>           0       0     FB4_7        67   I/O       I       RESET
regBtn<4>           2       7     FB4_1        60   I/O       I       RESET
regBtn<5>           2       7     FB4_2        61   I/O       I       RESET
regBtn<6>           0       0     FB4_3        62   I/O       I       RESET
regBtn<7>           0       0     FB7_4        53   I/O       I       RESET
regBtn<8>           0       0     FB7_3        54   I/O       I       RESET
regBtn<9>           0       0     FB7_2        55   I/O       I       RESET
regSsg<2>           2       8     FB1_9             (b)       (b)     RESET
regSsg<3>           2       8     FB1_8             (b)       (b)     RESET
regSsg<4>           2       8     FB1_16       91   I/O       I       RESET
regSsg<5>           2       8     FB1_14       93   I/O       I       RESET
regSsg<6>           2       8     FB1_13       94   I/O       I       RESET
regSsg<7>           2       8     FB1_12       96   I/O       I       RESET
regSsg<8>           2       8     FB1_2        104  TDO/I/O   (b)     RESET
regSsg<9>           2       8     FB1_10            (b)       (b)     RESET
rgbBtnOt<0>         1       1     FB2_6   SLOW 113  I/O       O       RESET
rgbBtnOt<1>         1       1     FB2_7   SLOW 114  I/O       O       RESET
rgbBtnOt<2>         1       1     FB2_11  SLOW 116  I/O       O       RESET
rgbBtnOt<3>         1       1     FB2_12  SLOW 117  I/O       O       RESET
rgbBtnOt<4>         1       1     FB2_13  SLOW 118  I/O       O       RESET
rgbBtnOt<5>         1       1     FB2_14  SLOW 119  I/O       O       RESET
rgbLcd<0>           2       3     FB5_13  SLOW 134  I/O       I/O     
rgbLcd<1>           2       3     FB5_12  SLOW 136  I/O       I/O     
rgbLcd<2>           2       3     FB5_11  SLOW 137  I/O       I/O     
rgbLcd<3>           2       3     FB5_7   SLOW 138  I/O       I/O     
rgbLcd<4>           2       3     FB5_6   SLOW 139  I/O       I/O     
rgbLcd<5>           2       3     FB5_5   SLOW 140  I/O       I/O     
rgbLcd<6>           2       3     FB5_4   SLOW 141  I/O       I/O     
rgbLcd<7>           2       3     FB5_3   SLOW 142  I/O       I/O     
rgbLed<0>           3       8     FB7_5   SLOW 46   I/O       O       SET
rgbLed<10>          3       8     FB8_15  SLOW 31   I/O       O       SET
rgbLed<11>          3       8     FB8_14  SLOW 30   I/O       O       SET
rgbLed<12>          3       8     FB8_13  SLOW 29   I/O       O       SET
rgbLed<13>          3       8     FB8_12  SLOW 28   I/O       O       SET
rgbLed<14>          3       8     FB8_11  SLOW 27   I/O       O       SET
rgbLed<15>          3       8     FB8_7   SLOW 26   I/O       O       SET
rgbLed<1>           3       8     FB7_6   SLOW 45   I/O       O       SET
rgbLed<2>           3       8     FB7_7   SLOW 44   I/O       O       SET
rgbLed<3>           3       8     FB7_11  SLOW 42   I/O       O       SET
rgbLed<4>           3       8     FB7_12  SLOW 41   I/O       O       SET
rgbLed<5>           3       8     FB7_13  SLOW 40   I/O       O       SET
rgbLed<6>           3       8     FB7_14  SLOW 39   I/O       O       SET
rgbLed<7>           3       8     FB7_15  SLOW 38   I/O       O       SET
rgbLed<8>           3       8     FB7_16  SLOW 37   I/O       O       SET
rgbLed<9>           3       8     FB8_16  SLOW 32   I/O       O       SET
rgbSsgAn<0>         1       2     FB6_7   SLOW 9    I/O       O       
rgbSsgAn<1>         1       2     FB6_11  SLOW 10   I/O       O       
rgbSsgAn<2>         1       2     FB6_12  SLOW 11   I/O       O       
rgbSsgAn<3>         1       2     FB6_13  SLOW 12   I/O       O       
rgbSsgCa<0>         7       15    FB8_6   SLOW 25   I/O       O       
rgbSsgCa<1>         10      17    FB8_5   SLOW 23   I/O       O       
rgbSsgCa<2>         6       15    FB8_4   SLOW 22   I/O       O       
rgbSsgCa<3>         10      17    FB8_3   SLOW 21   I/O       O       
rgbSsgCa<4>         9       16    FB8_1   SLOW 18   I/O       O       
rgbSsgCa<5>         9       17    FB6_16  SLOW 16   I/O       O       
rgbSsgCa<6>         8       17    FB6_15  SLOW 15   I/O       O       
rgbSsgCa<7>         0       0     FB6_14  SLOW 14   I/O       O       

** INPUTS **
Signal                            Loc          Pin  Pin       Pin      I/O 
Name                                           #    Type      Use     Style
adr<0>                            FB4_16       74   I/O       I                  
adr<1>                            FB3_15       78   I/O       I                  
adr<2>                            FB3_13       80   I/O       I                  
adr<3>                            FB3_11       82   I/O       I                  
adr<4>                            FB3_6        84   I/O       I                  
adr<5>                            FB3_4        87   I/O       I                  
clk                                            127  GCK/I     GCK                
cs                                FB1_14       93   I/O       I                  
kcin                              FB6_6        8    I/O       I                  
kdin                              FB6_5        7    I/O       I                  
lcen                              FB2_1        107  I/O       I                  
oe                                FB1_16       91   I/O       I                  
rgbBtnIn<0>                       FB4_12       69   I/O       I                  
rgbBtnIn<10>                      FB4_13       70   I/O       I                  
rgbBtnIn<11>                      FB4_14       71   I/O       I                  
rgbBtnIn<12>                      FB7_1        56   I/O       I                  
rgbBtnIn<13>                      FB4_4        63   I/O       I                  
rgbBtnIn<14>                      FB4_11       68   I/O       I                  
rgbBtnIn<15>                      FB4_15       72   I/O       I                  
rgbBtnIn<1>                       FB4_5        65   I/O       I                  
rgbBtnIn<2>                       FB4_6        66   I/O       I                  
rgbBtnIn<3>                       FB4_7        67   I/O       I                  
rgbBtnIn<4>                       FB4_1        60   I/O       I                  
rgbBtnIn<5>                       FB4_2        61   I/O       I                  
rgbBtnIn<6>                       FB4_3        62   I/O       I                  
rgbBtnIn<7>                       FB7_4        53   I/O       I                  
rgbBtnIn<8>                       FB7_3        54   I/O       I                  
rgbBtnIn<9>                       FB7_2        55   I/O       I                  
rgbSwt<0>                         FB1_3        102  I/O       I                  
rgbSwt<1>                         FB1_4        101  I/O       I                  
rgbSwt<2>                         FB1_5        100  I/O       I                  
rgbSwt<3>                         FB1_6        99   I/O       I                  
rgbSwt<4>                         FB1_7        98   I/O       I                  
rgbSwt<5>                         FB1_11       97   I/O       I                  
rgbSwt<6>                         FB1_12       96   I/O       I                  
rgbSwt<7>                         FB1_13       94   I/O       I                  
we                                             125  GCK/I     GCK/I              

End of Resources

Legend: PU  - Pull Up
*********************Function Block Resource Summary***********************
Function    # of        FB Inputs   Signals     Total       O/IO      IO    
Block       Macrocells  Used        Used        Pt Used     Req       Avail 
FB1          16          39          39           36         0/1       12   
FB2          16          25          25           32        12/0       13   
FB3           8          39          39           33         0/7       12   
FB4           7           7           7            4         0/0       13   
FB5          10          16          16           13         2/8       13   
FB6           8          21          21           22         8/0       12   
FB7          12          15          15           11         9/0       13   
FB8          12          39          39           47        12/0       12   
            ----                                -----       -----     ----- 
             89                                  198        43/16     100   
*********************************** FB1 ***********************************
Number of signals used by logic mapping into function block:  39
Number of function block inputs used/remaining:               39/1
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  2/6
Number of PLA product terms used/remaining:                   36/12
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
N_PZ_267                            4    FB1_1     106   I/O   (b)
regSsg<8>                           2    FB1_2     104TDO/I/O   (b)
N_PZ_258                            4    FB1_3     102   I/O     I
N_PZ_264                            4    FB1_4     101   I/O     I
dig<0>                              4    FB1_5     100   I/O     I
cntDig<1>                           1    FB1_6      99   I/O     I
cntDig<0>                           0    FB1_7      98   I/O     I
regSsg<3>                           2    FB1_8           (b)   (b)
regSsg<2>                           2    FB1_9           (b)   (b)
regSsg<9>                           2    FB1_10          (b)   (b)
N_PZ_229                            2    FB1_11     97   I/O     I
regSsg<7>                           2    FB1_12     96   I/O     I
regSsg<6>                           2    FB1_13     94   I/O     I
regSsg<5>                           2    FB1_14     93   I/O     I
db<7>                               6    FB1_15     92   I/O   I/O
regSsg<4>                           2    FB1_16     91   I/O     I

Signals Used by Logic in Function Block
  1: N_PZ_229          14: db<1>.PIN         27: oe 
  2: adr<0>            15: db<2>             28: regBtn<7> 
  3: adr<1>            16: db<2>.PIN         29: regSsg<2> 
  4: adr<2>            17: db<3>             30: regSsg<3> 
  5: adr<3>            18: db<3>.PIN         31: regSsg<4> 
  6: adr<4>            19: db<4>             32: regSsg<5> 
  7: adr<5>            20: db<4>.PIN         33: regSsg<6> 
  8: cntDig<0>         21: db<5>             34: regSsg<7> 
  9: cntDig<1>         22: db<5>.PIN         35: regSsg<8> 
 10: cs                23: db<6>             36: regSsg<9> 
 11: db<0>             24: db<6>.PIN         37: rgbBtnOt<5> 
 12: db<0>.PIN         25: db<7>             38: rgbLcd<7>.PIN 
 13: db<1>             26: db<7>.PIN         39: rgbSwt<7> 

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
N_PZ_267          .......XX...X.X.X...X.X.X...XX.XXX.X.... 14      14
regSsg<8>         .XXXXXX..X.X............................ 8       8
N_PZ_258          .......XX...X.X.X...X.X.X...XX.XXX.X.... 14      14
N_PZ_264          .......XX.....X.X.....X.X...XX..XX...... 10      10
dig<0>            .......XX.X.......X...........X...X..... 6       6
cntDig<1>         .......X................................ 1       1
cntDig<0>         ........................................ 0       0
regSsg<3>         .XXXXXX..X.......X...................... 8       8
regSsg<2>         .XXXXXX..X.....X........................ 8       8
regSsg<9>         .XXXXXX..X...X.......................... 8       8
N_PZ_229          .XXXXXX................................. 6       6
regSsg<7>         .XXXXXX..X...............X.............. 8       8
regSsg<6>         .XXXXXX..X.............X................ 8       8
regSsg<5>         .XXXXXX..X...........X.................. 8       8
db<7>             XXXXXXX..X................XX........XXX. 13      13
regSsg<4>         .XXXXXX..X.........X.................... 8       8
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB2 ***********************************
Number of signals used by logic mapping into function block:  25
Number of function block inputs used/remaining:               25/15
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  1/7
Number of PLA product terms used/remaining:                   32/16
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
N_PZ_302                            2    FB2_1     107   I/O     I
encBtn<0>                           5    FB2_2     109   I/O     O
encBtn<1>                           5    FB2_3     110   I/O     O
encBtn<2>                           5    FB2_4     111   I/O     O
encBtn<3>                           1    FB2_5     112   I/O     O
rgbBtnOt<0>                         1    FB2_6     113   I/O     O
rgbBtnOt<1>                         1    FB2_7     114   I/O     O
N_PZ_232                            2    FB2_8           (b)   (b)
N_PZ_230                            2    FB2_9           (b)   (b)
N_PZ_283                            1    FB2_10          (b)   (b)
rgbBtnOt<2>                         1    FB2_11    116   I/O     O
rgbBtnOt<3>                         1    FB2_12    117   I/O     O
rgbBtnOt<4>                         1    FB2_13    118   I/O     O
rgbBtnOt<5>                         1    FB2_14    119   I/O     O
kclk                                1    FB2_15    120   I/O     O
kdat                                1    FB2_16    121   I/O     O

Signals Used by Logic in Function Block
  1: cntDig<0>         10: regBtn<5>         18: regSsg<6> 
  2: db<1>             11: regBtn<6>         19: regSsg<7> 
  3: kcin              12: regBtn<7>         20: rgbBtnIn<10> 
  4: kdin              13: regBtn<8>         21: rgbBtnIn<11> 
  5: regBtn<0>         14: regBtn<9>         22: rgbBtnIn<12> 
  6: regBtn<1>         15: regSsg<2>         23: rgbBtnIn<13> 
  7: regBtn<2>         16: regSsg<3>         24: rgbBtnIn<14> 
  8: regBtn<3>         17: regSsg<5>         25: rgbBtnIn<15> 
  9: regBtn<4>        

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
N_PZ_302          XX............XXXXX..................... 7       7
encBtn<0>         ....XXXXXXXXX........................... 9       9
encBtn<1>         ....XXXXXXXXXX.......................... 10      10
encBtn<2>         ....XXXXXXXXXX.......................... 10      10
encBtn<3>         ....XXXXXXXX............................ 8       8
rgbBtnOt<0>       ...................X.................... 1       1
rgbBtnOt<1>       ....................X................... 1       1
N_PZ_232          XX............XXXXX..................... 7       7
N_PZ_230          XX............XXXXX..................... 7       7
N_PZ_283          ................XX...................... 2       2
rgbBtnOt<2>       .....................X.................. 1       1
rgbBtnOt<3>       ......................X................. 1       1
rgbBtnOt<4>       .......................X................ 1       1
rgbBtnOt<5>       ........................X............... 1       1
kclk              ..X..................................... 1       1
kdat              ...X.................................... 1       1
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB3 ***********************************
Number of signals used by logic mapping into function block:  39
Number of function block inputs used/remaining:               39/1
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  2/6
Number of PLA product terms used/remaining:                   33/15
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
db<6>                               6    FB3_1      90   I/O   I/O
N_PZ_335                            1    FB3_2      89TCK/I/O   (b)
db<5>                               6    FB3_3      88   I/O   I/O
(unused)                            0    FB3_4      87   I/O     I
db<4>                               6    FB3_5      86   I/O   I/O
(unused)                            0    FB3_6      84   I/O     I
db<3>                               6    FB3_7      83   I/O   I/O
(unused)                            0    FB3_8           (b)      
(unused)                            0    FB3_9           (b)      
(unused)                            0    FB3_10          (b)      
(unused)                            0    FB3_11     82   I/O     I
db<2>                               6    FB3_12     81   I/O   I/O
(unused)                            0    FB3_13     80   I/O     I
db<1>                               6    FB3_14     79   I/O   I/O
(unused)                            0    FB3_15     78   I/O     I
db<0>                               6    FB3_16     77   I/O   I/O

Signals Used by Logic in Function Block
  1: N_PZ_229          14: regBtn<3>         27: rgbLcd<1>.PIN 
  2: adr<0>            15: regBtn<4>         28: rgbLcd<2>.PIN 
  3: adr<1>            16: regBtn<5>         29: rgbLcd<3>.PIN 
  4: adr<2>            17: regBtn<6>         30: rgbLcd<4>.PIN 
  5: adr<3>            18: regBtn<8>         31: rgbLcd<5>.PIN 
  6: adr<4>            19: regBtn<9>         32: rgbLcd<6>.PIN 
  7: adr<5>            20: regSsg<9>         33: rgbSwt<0> 
  8: cs                21: rgbBtnOt<0>       34: rgbSwt<1> 
  9: db<2>             22: rgbBtnOt<1>       35: rgbSwt<2> 
 10: oe                23: rgbBtnOt<2>       36: rgbSwt<3> 
 11: regBtn<0>         24: rgbBtnOt<3>       37: rgbSwt<4> 
 12: regBtn<1>         25: rgbBtnOt<4>       38: rgbSwt<5> 
 13: regBtn<2>         26: rgbLcd<0>.PIN     39: rgbSwt<6> 

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
db<6>             XXXXXXXX.X......X.......X......X......X. 13      13
N_PZ_335          ........X..........X.................... 2       2
db<5>             XXXXXXXX.X.....X.......X......X......X.. 13      13
db<4>             XXXXXXXX.X....X.......X......X......X... 13      13
db<3>             XXXXXXXX.X...X.......X......X......X.... 13      13
db<2>             XXXXXXXX.X..X.......X......X......X..... 13      13
db<1>             XXXXXXXX.X.X......X.......X......X...... 13      13
db<0>             XXXXXXXX.XX......X.......X......X....... 13      13
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB4 ***********************************
Number of signals used by logic mapping into function block:  7
Number of function block inputs used/remaining:               7/33
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   4/44
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
regBtn<4>                           2    FB4_1      60   I/O     I
regBtn<5>                           2    FB4_2      61   I/O     I
regBtn<6>                           0    FB4_3      62   I/O     I
(unused)                            0    FB4_4      63   I/O     I
regBtn<1>                           0    FB4_5      65   I/O     I
regBtn<2>                           0    FB4_6      66   I/O     I
regBtn<3>                           0    FB4_7      67   I/O     I
(unused)                            0    FB4_8           (b)      
(unused)                            0    FB4_9           (b)      
(unused)                            0    FB4_10          (b)      
(unused)                            0    FB4_11     68   I/O     I
regBtn<0>                           0    FB4_12     69   I/O     I
(unused)                            0    FB4_13     70   I/O     I
(unused)                            0    FB4_14     71   I/O     I
(unused)                            0    FB4_15     72   I/O     I
(unused)                            0    FB4_16     74   I/O     I

Signals Used by Logic in Function Block
  1: cntDig<0>          4: db<5>              6: db<7> 
  2: db<2>              5: db<6>              7: regSsg<9> 
  3: db<3>            

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
regBtn<4>         XXXXXXX................................. 7       7
regBtn<5>         XXXXXXX................................. 7       7
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB5 ***********************************
Number of signals used by logic mapping into function block:  16
Number of function block inputs used/remaining:               16/24
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  1/7
Number of PLA product terms used/remaining:                   13/35
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
lcdrw                               1    FB5_1       1   I/O     O
lcden                               3    FB5_2     143   I/O     O
rgbLcd<7>                           2    FB5_3     142   I/O   I/O
rgbLcd<6>                           2    FB5_4     141   I/O   I/O
rgbLcd<5>                           2    FB5_5     140   I/O   I/O
rgbLcd<4>                           2    FB5_6     139   I/O   I/O
rgbLcd<3>                           2    FB5_7     138   I/O   I/O
(unused)                            0    FB5_8           (b)      
(unused)                            0    FB5_9           (b)      
(unused)                            0    FB5_10          (b)      
rgbLcd<2>                           2    FB5_11    137   I/O   I/O
rgbLcd<1>                           2    FB5_12    136   I/O   I/O
rgbLcd<0>                           2    FB5_13    134   I/O   I/O
(unused)                            0    FB5_14    133   I/O      
(unused)                            0    FB5_15    132   I/O      
(unused)                            0    FB5_16    131   I/O      

Signals Used by Logic in Function Block
  1: adr<2>             7: db<1>.PIN         12: db<6>.PIN 
  2: adr<3>             8: db<2>.PIN         13: db<7>.PIN 
  3: adr<4>             9: db<3>.PIN         14: lcen 
  4: adr<5>            10: db<4>.PIN         15: oe 
  5: cs                11: db<5>.PIN         16: we 
  6: db<0>.PIN        

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
lcdrw             ...............X........................ 1       1
lcden             XXXXX........XXX........................ 8       8
rgbLcd<7>         ....X.......X..X........................ 3       3
rgbLcd<6>         ....X......X...X........................ 3       3
rgbLcd<5>         ....X.....X....X........................ 3       3
rgbLcd<4>         ....X....X.....X........................ 3       3
rgbLcd<3>         ....X...X......X........................ 3       3
rgbLcd<2>         ....X..X.......X........................ 3       3
rgbLcd<1>         ....X.X........X........................ 3       3
rgbLcd<0>         ....XX.........X........................ 3       3
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB6 ***********************************
Number of signals used by logic mapping into function block:  21
Number of function block inputs used/remaining:               21/19
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   22/26
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
lcdrs                               1    FB6_1       2   I/O     O
(unused)                            0    FB6_2       4TDI/I/O      
(unused)                            0    FB6_3       5   I/O      
(unused)                            0    FB6_4       6   I/O      
(unused)                            0    FB6_5       7   I/O     I
(unused)                            0    FB6_6       8   I/O     I
rgbSsgAn<0>                         1    FB6_7       9   I/O     O
(unused)                            0    FB6_8           (b)      
(unused)                            0    FB6_9           (b)      
(unused)                            0    FB6_10          (b)      
rgbSsgAn<1>                         1    FB6_11     10   I/O     O
rgbSsgAn<2>                         1    FB6_12     11   I/O     O
rgbSsgAn<3>                         1    FB6_13     12   I/O     O
rgbSsgCa<7>                         0    FB6_14     14   I/O     O
rgbSsgCa<6>                         8    FB6_15     15   I/O     O
rgbSsgCa<5>                         9    FB6_16     16   I/O     O

Signals Used by Logic in Function Block
  1: N_PZ_230           8: cntDig<1>         15: regBtn<4>.COMB 
  2: N_PZ_232           9: db<1>             16: regBtn<5>.COMB 
  3: N_PZ_267          10: db<3>             17: regSsg<2> 
  4: N_PZ_283          11: db<5>             18: regSsg<3> 
  5: N_PZ_335          12: db<6>             19: regSsg<6> 
  6: adr<0>            13: db<7>             20: regSsg<7> 
  7: cntDig<0>         14: dig<0>            21: regSsg<9> 

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
lcdrs             .....X.................................. 1       1
rgbSsgAn<0>       ......XX................................ 2       2
rgbSsgAn<1>       ......XX................................ 2       2
rgbSsgAn<2>       ......XX................................ 2       2
rgbSsgAn<3>       ......XX................................ 2       2
rgbSsgCa<7>       ........................................ 0       0
rgbSsgCa<6>       XX.XX.XXXXXXXXXXXX.X.................... 17      17
rgbSsgCa<5>       X.XX..XXXXX.XXXXXXXXX................... 17      17
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB7 ***********************************
Number of signals used by logic mapping into function block:  15
Number of function block inputs used/remaining:               15/25
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  1/7
Number of PLA product terms used/remaining:                   11/37
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
(unused)                            0    FB7_1      56   I/O     I
regBtn<9>                           0    FB7_2      55   I/O     I
regBtn<8>                           0    FB7_3      54   I/O     I
regBtn<7>                           0    FB7_4      53   I/O     I
rgbLed<0>                           3    FB7_5      46   I/O     O
rgbLed<1>                           3    FB7_6      45   I/O     O
rgbLed<2>                           3    FB7_7      44   I/O     O
(unused)                            0    FB7_8           (b)      
(unused)                            0    FB7_9           (b)      
(unused)                            0    FB7_10          (b)      
rgbLed<3>                           3    FB7_11     42   I/O     O
rgbLed<4>                           3    FB7_12     41   I/O     O
rgbLed<5>                           3    FB7_13     40   I/O     O
rgbLed<6>                           3    FB7_14     39   I/O     O
rgbLed<7>                           3    FB7_15     38   I/O     O
rgbLed<8>                           3    FB7_16     37   I/O     O

Signals Used by Logic in Function Block
  1: adr<0>             6: adr<5>            11: db<3>.PIN 
  2: adr<1>             7: cs                12: db<4>.PIN 
  3: adr<2>             8: db<0>.PIN         13: db<5>.PIN 
  4: adr<3>             9: db<1>.PIN         14: db<6>.PIN 
  5: adr<4>            10: db<2>.PIN         15: db<7>.PIN 

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
rgbLed<0>         XXXXXXXX................................ 8       8
rgbLed<1>         XXXXXXX.X............................... 8       8
rgbLed<2>         XXXXXXX..X.............................. 8       8
rgbLed<3>         XXXXXXX...X............................. 8       8
rgbLed<4>         XXXXXXX....X............................ 8       8
rgbLed<5>         XXXXXXX.....X........................... 8       8
rgbLed<6>         XXXXXXX......X.......................... 8       8
rgbLed<7>         XXXXXXX.......X......................... 8       8
rgbLed<8>         XXXXXXXX................................ 8       8
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB8 ***********************************
Number of signals used by logic mapping into function block:  39
Number of function block inputs used/remaining:               39/1
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  1/7
Number of PLA product terms used/remaining:                   47/1
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
rgbSsgCa<4>                         9    FB8_1      18   I/O     O
(unused)                            0    FB8_2      20TMS/I/O      
rgbSsgCa<3>                        10    FB8_3      21   I/O     O
rgbSsgCa<2>                         6    FB8_4      22   I/O     O
rgbSsgCa<1>                        10    FB8_5      23   I/O     O
rgbSsgCa<0>                         7    FB8_6      25   I/O     O
rgbLed<15>                          3    FB8_7      26   I/O     O
(unused)                            0    FB8_8           (b)      
(unused)                            0    FB8_9           (b)      
(unused)                            0    FB8_10          (b)      
rgbLed<14>                          3    FB8_11     27   I/O     O
rgbLed<13>                          3    FB8_12     28   I/O     O
rgbLed<12>                          3    FB8_13     29   I/O     O
rgbLed<11>                          3    FB8_14     30   I/O     O
rgbLed<10>                          3    FB8_15     31   I/O     O
rgbLed<9>                           3    FB8_16     32   I/O     O

Signals Used by Logic in Function Block
  1: N_PZ_230          14: adr<5>            27: db<6> 
  2: N_PZ_232          15: cntDig<0>         28: db<6>.PIN 
  3: N_PZ_258          16: cntDig<1>         29: db<7> 
  4: N_PZ_264          17: cs                30: db<7>.PIN 
  5: N_PZ_267          18: db<1>             31: dig<0> 
  6: N_PZ_283          19: db<1>.PIN         32: regBtn<4>.COMB 
  7: N_PZ_302          20: db<2>             33: regBtn<5>.COMB 
  8: N_PZ_335          21: db<2>.PIN         34: regSsg<2> 
  9: adr<0>            22: db<3>             35: regSsg<3> 
 10: adr<1>            23: db<3>.PIN         36: regSsg<5> 
 11: adr<2>            24: db<4>.PIN         37: regSsg<6> 
 12: adr<3>            25: db<5>             38: regSsg<7> 
 13: adr<4>            26: db<5>.PIN         39: regSsg<9> 

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
rgbSsgCa<4>       ..X...........XX.X.X.X..X.X.X.X..XXXXXX. 16      16
rgbSsgCa<3>       .XX..XXX......XX.X.X.X..X.X.X.X.XX....X. 17      17
rgbSsgCa<2>       ...XXX.X......XX.X...X..X.X.X.X..XX..X.. 15      15
rgbSsgCa<1>       ..XX.X.X......XX.X...X..X.X.X.X..XXX.XX. 17      17
rgbSsgCa<0>       XXX...X.......XX...X.X..X.X.X.XXX.....X. 15      15
rgbLed<15>        ........XXXXXX..X............X.......... 8       8
rgbLed<14>        ........XXXXXX..X..........X............ 8       8
rgbLed<13>        ........XXXXXX..X........X.............. 8       8
rgbLed<12>        ........XXXXXX..X......X................ 8       8
rgbLed<11>        ........XXXXXX..X.....X................. 8       8
rgbLed<10>        ........XXXXXX..X...X................... 8       8
rgbLed<9>         ........XXXXXX..X.X..................... 8       8
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
;;-----------------------------------------------------------------;;
; Implemented Equations.


encBtn(0) <= ((NOT regBtn(0) AND regBtn(1))
	OR (NOT regBtn(0) AND NOT regBtn(2) AND regBtn(3))
	OR (NOT regBtn(0) AND NOT regBtn(4) AND regBtn(5) AND NOT regBtn(2))
	OR (NOT regBtn(0) AND NOT regBtn(4) AND NOT regBtn(2) AND NOT regBtn(6) AND 
	regBtn(7))
	OR (NOT regBtn(0) AND NOT regBtn(4) AND NOT regBtn(2) AND NOT regBtn(6) AND 
	NOT regBtn(8)));

FDCPE_regBtn0: FDCPE port map (regBtn(0),rgbBtnIn(0),clk,'0','0','1');

FDCPE_regBtn1: FDCPE port map (regBtn(1),rgbBtnIn(1),clk,'0','0','1');


regBtn(4).COMB <= ((cntDig(0) AND regSsg(10) AND regSsg(11) AND NOT regSsg(9))
	OR (NOT cntDig(0) AND NOT regSsg(13) AND regSsg(14) AND 
	regSsg(15)));FDCPE_regBtn4: FDCPE port map (regBtn(4),rgbBtnIn(4),clk,'0','0','1');


regBtn(5).COMB <= ((cntDig(0) AND NOT regSsg(10) AND NOT regSsg(11) AND NOT regSsg(9))
	OR (NOT cntDig(0) AND NOT regSsg(13) AND NOT regSsg(14) AND 
	NOT regSsg(15)));FDCPE_regBtn5: FDCPE port map (regBtn(5),rgbBtnIn(5),clk,'0','0','1');

FDCPE_regBtn2: FDCPE port map (regBtn(2),rgbBtnIn(2),clk,'0','0','1');

FDCPE_regBtn3: FDCPE port map (regBtn(3),rgbBtnIn(3),clk,'0','0','1');

FDCPE_regBtn6: FDCPE port map (regBtn(6),rgbBtnIn(6),clk,'0','0','1');

FDCPE_regBtn7: FDCPE port map (regBtn(7),rgbBtnIn(7),clk,'0','0','1');

FDCPE_regBtn8: FDCPE port map (regBtn(8),rgbBtnIn(8),clk,'0','0','1');


encBtn(1) <= ((NOT regBtn(0) AND NOT regBtn(1) AND regBtn(2))
	OR (NOT regBtn(0) AND NOT regBtn(1) AND regBtn(3))
	OR (NOT regBtn(0) AND NOT regBtn(1) AND NOT regBtn(4) AND NOT regBtn(5) AND 
	regBtn(6))
	OR (NOT regBtn(0) AND NOT regBtn(1) AND NOT regBtn(4) AND NOT regBtn(5) AND 
	regBtn(7))
	OR (NOT regBtn(0) AND NOT regBtn(1) AND NOT regBtn(4) AND NOT regBtn(5) AND 
	NOT regBtn(8) AND NOT regBtn(9)));

FDCPE_regBtn9: FDCPE port map (regBtn(9),rgbBtnIn(9),clk,'0','0','1');


encBtn(2) <= ((NOT regBtn(0) AND NOT regBtn(1) AND regBtn(4) AND NOT regBtn(2) AND 
	NOT regBtn(3))
	OR (NOT regBtn(0) AND NOT regBtn(1) AND regBtn(5) AND NOT regBtn(2) AND 
	NOT regBtn(3))
	OR (NOT regBtn(0) AND NOT regBtn(1) AND NOT regBtn(2) AND NOT regBtn(3) AND 
	regBtn(6))
	OR (NOT regBtn(0) AND NOT regBtn(1) AND NOT regBtn(2) AND NOT regBtn(3) AND 
	regBtn(7))
	OR (NOT regBtn(0) AND NOT regBtn(1) AND NOT regBtn(2) AND NOT regBtn(3) AND 
	NOT regBtn(8) AND NOT regBtn(9)));


encBtn(3) <= (NOT regBtn(0) AND NOT regBtn(1) AND NOT regBtn(4) AND NOT regBtn(5) AND 
	NOT regBtn(2) AND NOT regBtn(3) AND NOT regBtn(6) AND NOT regBtn(7));


kclk <= kcin;


kdat <= kdin;


lcden <= ((lcen)
	OR (NOT adr(5) AND NOT adr(4) AND NOT adr(3) AND NOT we AND adr(2) AND NOT cs)
	OR (NOT adr(5) AND NOT adr(4) AND NOT adr(3) AND adr(2) AND NOT cs AND NOT oe));


lcdrs <= adr(0);


lcdrw <= we;

FDCPE_rgbBtnOt0: FDCPE port map (rgbBtnOt(0),rgbBtnIn(10),clk,'0','0','1');

FDCPE_rgbBtnOt1: FDCPE port map (rgbBtnOt(1),rgbBtnIn(11),clk,'0','0','1');

FDCPE_rgbBtnOt2: FDCPE port map (rgbBtnOt(2),rgbBtnIn(12),clk,'0','0','1');

FDCPE_rgbBtnOt3: FDCPE port map (rgbBtnOt(3),rgbBtnIn(13),clk,'0','0','1');

FDCPE_rgbBtnOt4: FDCPE port map (rgbBtnOt(4),rgbBtnIn(14),clk,'0','0','1');

FDCPE_rgbBtnOt5: FDCPE port map (rgbBtnOt(5),rgbBtnIn(15),clk,'0','0','1');


rgbLcd_I(0) <= db(0).PIN;
rgbLcd(0) <= rgbLcd_I(0) when rgbLcd_OE(0) = '1' else 'Z';
rgbLcd_OE(0) <= (NOT we AND NOT cs);


rgbLcd_I(1) <= db(1).PIN;
rgbLcd(1) <= rgbLcd_I(1) when rgbLcd_OE(1) = '1' else 'Z';
rgbLcd_OE(1) <= (NOT we AND NOT cs);


rgbLcd_I(2) <= db(2).PIN;
rgbLcd(2) <= rgbLcd_I(2) when rgbLcd_OE(2) = '1' else 'Z';
rgbLcd_OE(2) <= (NOT we AND NOT cs);


rgbLcd_I(3) <= db(3).PIN;
rgbLcd(3) <= rgbLcd_I(3) when rgbLcd_OE(3) = '1' else 'Z';
rgbLcd_OE(3) <= (NOT we AND NOT cs);


rgbLcd_I(4) <= db(4).PIN;
rgbLcd(4) <= rgbLcd_I(4) when rgbLcd_OE(4) = '1' else 'Z';
rgbLcd_OE(4) <= (NOT we AND NOT cs);


rgbLcd_I(5) <= db(5).PIN;
rgbLcd(5) <= rgbLcd_I(5) when rgbLcd_OE(5) = '1' else 'Z';
rgbLcd_OE(5) <= (NOT we AND NOT cs);


rgbLcd_I(6) <= db(6).PIN;
rgbLcd(6) <= rgbLcd_I(6) when rgbLcd_OE(6) = '1' else 'Z';
rgbLcd_OE(6) <= (NOT we AND NOT cs);


rgbLcd_I(7) <= db(7).PIN;
rgbLcd(7) <= rgbLcd_I(7) when rgbLcd_OE(7) = '1' else 'Z';
rgbLcd_OE(7) <= (NOT we AND NOT cs);

FDCPE_rgbLed0: FDCPE port map (rgbLed(0),NOT db(0).PIN,we,'0',NOT ,rgbLed_CE(0));
rgbLed_CE(0) <= (NOT adr(5) AND NOT adr(4) AND NOT adr(3) AND NOT adr(2) AND NOT cs AND 
	NOT adr(0) AND NOT adr(1));

FDCPE_rgbLed10: FDCPE port map (rgbLed(10),NOT db(2).PIN,we,'0',NOT ,rgbLed_CE(10));
rgbLed_CE(10) <= (NOT adr(5) AND NOT adr(4) AND NOT adr(3) AND NOT adr(2) AND NOT cs AND 
	adr(0) AND NOT adr(1));

FDCPE_rgbLed11: FDCPE port map (rgbLed(11),NOT db(3).PIN,we,'0',NOT ,rgbLed_CE(11));
rgbLed_CE(11) <= (NOT adr(5) AND NOT adr(4) AND NOT adr(3) AND NOT adr(2) AND NOT cs AND 
	adr(0) AND NOT adr(1));

FDCPE_rgbLed12: FDCPE port map (rgbLed(12),NOT db(4).PIN,we,'0',NOT ,rgbLed_CE(12));
rgbLed_CE(12) <= (NOT adr(5) AND NOT adr(4) AND NOT adr(3) AND NOT adr(2) AND NOT cs AND 
	adr(0) AND NOT adr(1));

FDCPE_rgbLed13: FDCPE port map (rgbLed(13),NOT db(5).PIN,we,'0',NOT ,rgbLed_CE(13));
rgbLed_CE(13) <= (NOT adr(5) AND NOT adr(4) AND NOT adr(3) AND NOT adr(2) AND NOT cs AND 
	adr(0) AND NOT adr(1));

FDCPE_rgbLed14: FDCPE port map (rgbLed(14),NOT db(6).PIN,we,'0',NOT ,rgbLed_CE(14));
rgbLed_CE(14) <= (NOT adr(5) AND NOT adr(4) AND NOT adr(3) AND NOT adr(2) AND NOT cs AND 
	adr(0) AND NOT adr(1));

FDCPE_rgbLed15: FDCPE port map (rgbLed(15),NOT db(7).PIN,we,'0',NOT ,rgbLed_CE(15));
rgbLed_CE(15) <= (NOT adr(5) AND NOT adr(4) AND NOT adr(3) AND NOT adr(2) AND NOT cs AND 
	adr(0) AND NOT adr(1));

FDCPE_rgbLed1: FDCPE port map (rgbLed(1),NOT db(1).PIN,we,'0',NOT ,rgbLed_CE(1));
rgbLed_CE(1) <= (NOT adr(5) AND NOT adr(4) AND NOT adr(3) AND NOT adr(2) AND NOT cs AND 
	NOT adr(0) AND NOT adr(1));

FDCPE_rgbLed2: FDCPE port map (rgbLed(2),NOT db(2).PIN,we,'0',NOT ,rgbLed_CE(2));
rgbLed_CE(2) <= (NOT adr(5) AND NOT adr(4) AND NOT adr(3) AND NOT adr(2) AND NOT cs AND 
	NOT adr(0) AND NOT adr(1));

FDCPE_rgbLed3: FDCPE port map (rgbLed(3),NOT db(3).PIN,we,'0',NOT ,rgbLed_CE(3));
rgbLed_CE(3) <= (NOT adr(5) AND NOT adr(4) AND NOT adr(3) AND NOT adr(2) AND NOT cs AND 
	NOT adr(0) AND NOT adr(1));

FDCPE_rgbLed4: FDCPE port map (rgbLed(4),NOT db(4).PIN,we,'0',NOT ,rgbLed_CE(4));
rgbLed_CE(4) <= (NOT adr(5) AND NOT adr(4) AND NOT adr(3) AND NOT adr(2) AND NOT cs AND 
	NOT adr(0) AND NOT adr(1));

FDCPE_rgbLed5: FDCPE port map (rgbLed(5),NOT db(5).PIN,we,'0',NOT ,rgbLed_CE(5));
rgbLed_CE(5) <= (NOT adr(5) AND NOT adr(4) AND NOT adr(3) AND NOT adr(2) AND NOT cs AND 
	NOT adr(0) AND NOT adr(1));

FDCPE_rgbLed6: FDCPE port map (rgbLed(6),NOT db(6).PIN,we,'0',NOT ,rgbLed_CE(6));
rgbLed_CE(6) <= (NOT adr(5) AND NOT adr(4) AND NOT adr(3) AND NOT adr(2) AND NOT cs AND 
	NOT adr(0) AND NOT adr(1));

FDCPE_rgbLed7: FDCPE port map (rgbLed(7),NOT db(7).PIN,we,'0',NOT ,rgbLed_CE(7));
rgbLed_CE(7) <= (NOT adr(5) AND NOT adr(4) AND NOT adr(3) AND NOT adr(2) AND NOT cs AND 
	NOT adr(0) AND NOT adr(1));

FDCPE_rgbLed8: FDCPE port map (rgbLed(8),NOT db(0).PIN,we,'0',NOT ,rgbLed_CE(8));
rgbLed_CE(8) <= (NOT adr(5) AND NOT adr(4) AND NOT adr(3) AND NOT adr(2) AND NOT cs AND 
	adr(0) AND NOT adr(1));

FDCPE_rgbLed9: FDCPE port map (rgbLed(9),NOT db(1).PIN,we,'0',NOT ,rgbLed_CE(9));
rgbLed_CE(9) <= (NOT adr(5) AND NOT adr(4) AND NOT adr(3) AND NOT adr(2) AND NOT cs AND 
	adr(0) AND NOT adr(1));


rgbSsgAn(0) <= NOT ((NOT cntDig(0) AND NOT cntDig(1)));

FTCPE_cntDig0: FTCPE port map (cntDig(0),'1',clk,'0','0','1');

FTCPE_cntDig1: FTCPE port map (cntDig(1),cntDig(0),clk,'0','0','1');


rgbSsgAn(1) <= NOT ((cntDig(0) AND NOT cntDig(1)));


rgbSsgAn(2) <= NOT ((NOT cntDig(0) AND cntDig(1)));


rgbSsgAn(3) <= NOT ((cntDig(0) AND cntDig(1)));


rgbSsgCa(0) <= (cntDig(1) AND dig(0))
	XOR ((NOT dig(0) AND N_PZ_258)
	OR (NOT cntDig(1) AND dig(0) AND regBtn(4).COMB)
	OR (NOT cntDig(1) AND dig(0) AND regBtn(5).COMB)
	OR (cntDig(1) AND dig(0) AND NOT N_PZ_230 AND NOT N_PZ_232 AND 
	NOT N_PZ_302)
	OR (cntDig(0) AND NOT cntDig(1) AND dig(0) AND NOT regSsg(10) AND 
	regSsg(11) AND regSsg(9))
	OR (NOT cntDig(0) AND NOT cntDig(1) AND dig(0) AND regSsg(13) AND 
	NOT regSsg(14) AND regSsg(15)));


dig(0) <= ((cntDig(0) AND cntDig(1) AND regSsg(0))
	OR (cntDig(0) AND NOT cntDig(1) AND regSsg(8))
	OR (NOT cntDig(0) AND cntDig(1) AND regSsg(4))
	OR (NOT cntDig(0) AND NOT cntDig(1) AND regSsg(12)));


db(0) <= ((rgbLcd(0).PIN AND NOT N_PZ_229)
	OR (regBtn(0) AND NOT adr(5) AND NOT adr(4) AND NOT adr(3) AND NOT adr(2) AND 
	NOT adr(0) AND NOT adr(1))
	OR (regBtn(8) AND NOT adr(5) AND NOT adr(4) AND NOT adr(3) AND NOT adr(2) AND 
	adr(0) AND NOT adr(1))
	OR (NOT adr(5) AND NOT adr(4) AND NOT adr(3) AND NOT adr(2) AND NOT adr(0) AND 
	adr(1) AND rgbSwt(0)));
db(0) <= db_I(0) when db_OE(0) = '1' else 'Z';
db_OE(0) <= (NOT cs AND NOT oe);FDCPE_regSsg0: FDCPE port map (regSsg(0),db(0).PIN,we,'0','0',regSsg_CE(0));
regSsg_CE(0) <= (NOT adr(5) AND NOT adr(4) AND NOT adr(3) AND NOT adr(2) AND NOT cs AND 
	NOT adr(0) AND adr(1));

FDCPE_regSsg4: FDCPE port map (regSsg(4),db(4).PIN,we,'0','0',regSsg_CE(4));
regSsg_CE(4) <= (NOT adr(5) AND NOT adr(4) AND NOT adr(3) AND NOT adr(2) AND NOT cs AND 
	NOT adr(0) AND adr(1));

FDCPE_regSsg8: FDCPE port map (regSsg(8),db(0).PIN,we,'0','0',regSsg_CE(8));
regSsg_CE(8) <= (NOT adr(5) AND NOT adr(4) AND NOT adr(3) AND NOT adr(2) AND NOT cs AND 
	adr(0) AND adr(1));


db(4) <= ((NOT N_PZ_229 AND rgbLcd(4).PIN)
	OR (regBtn(4) AND NOT adr(5) AND NOT adr(4) AND NOT adr(3) AND NOT adr(2) AND 
	NOT adr(0) AND NOT adr(1))
	OR (NOT adr(5) AND NOT adr(4) AND NOT adr(3) AND NOT adr(2) AND adr(0) AND 
	NOT adr(1) AND rgbBtnOt(2))
	OR (NOT adr(5) AND NOT adr(4) AND NOT adr(3) AND NOT adr(2) AND NOT adr(0) AND 
	adr(1) AND rgbSwt(4)));
db(4) <= db_I(4) when db_OE(4) = '1' else 'Z';
db_OE(4) <= (NOT cs AND NOT oe);FDCPE_regSsg12: FDCPE port map (regSsg(12),db(4).PIN,we,'0','0',regSsg_CE(12));
regSsg_CE(12) <= (NOT adr(5) AND NOT adr(4) AND NOT adr(3) AND NOT adr(2) AND NOT cs AND 
	adr(0) AND adr(1));


db(2) <= ((NOT N_PZ_229 AND rgbLcd(2).PIN)
	OR (regBtn(2) AND NOT adr(5) AND NOT adr(4) AND NOT adr(3) AND NOT adr(2) AND 
	NOT adr(0) AND NOT adr(1))
	OR (NOT adr(5) AND NOT adr(4) AND NOT adr(3) AND NOT adr(2) AND adr(0) AND 
	NOT adr(1) AND rgbBtnOt(0))
	OR (NOT adr(5) AND NOT adr(4) AND NOT adr(3) AND NOT adr(2) AND NOT adr(0) AND 
	adr(1) AND rgbSwt(2)));
db(2) <= db_I(2) when db_OE(2) = '1' else 'Z';
db_OE(2) <= (NOT cs AND NOT oe);FDCPE_regSsg10: FDCPE port map (regSsg(10),db(2).PIN,we,'0','0',regSsg_CE(10));
regSsg_CE(10) <= (NOT adr(5) AND NOT adr(4) AND NOT adr(3) AND NOT adr(2) AND NOT cs AND 
	adr(0) AND adr(1));


db(3) <= ((NOT N_PZ_229 AND rgbLcd(3).PIN)
	OR (regBtn(3) AND NOT adr(5) AND NOT adr(4) AND NOT adr(3) AND NOT adr(2) AND 
	NOT adr(0) AND NOT adr(1))
	OR (NOT adr(5) AND NOT adr(4) AND NOT adr(3) AND NOT adr(2) AND adr(0) AND 
	NOT adr(1) AND rgbBtnOt(1))
	OR (NOT adr(5) AND NOT adr(4) AND NOT adr(3) AND NOT adr(2) AND NOT adr(0) AND 
	adr(1) AND rgbSwt(3)));
db(3) <= db_I(3) when db_OE(3) = '1' else 'Z';
db_OE(3) <= (NOT cs AND NOT oe);FDCPE_regSsg11: FDCPE port map (regSsg(11),db(3).PIN,we,'0','0',regSsg_CE(11));
regSsg_CE(11) <= (NOT adr(5) AND NOT adr(4) AND NOT adr(3) AND NOT adr(2) AND NOT cs AND 
	adr(0) AND adr(1));

FDCPE_regSsg9: FDCPE port map (regSsg(9),db(1).PIN,we,'0','0',regSsg_CE(9));
regSsg_CE(9) <= (NOT adr(5) AND NOT adr(4) AND NOT adr(3) AND NOT adr(2) AND NOT cs AND 
	adr(0) AND adr(1));


db(5) <= ((NOT N_PZ_229 AND rgbLcd(5).PIN)
	OR (regBtn(5) AND NOT adr(5) AND NOT adr(4) AND NOT adr(3) AND NOT adr(2) AND 
	NOT adr(0) AND NOT adr(1))
	OR (NOT adr(5) AND NOT adr(4) AND NOT adr(3) AND NOT adr(2) AND adr(0) AND 
	NOT adr(1) AND rgbBtnOt(3))
	OR (NOT adr(5) AND NOT adr(4) AND NOT adr(3) AND NOT adr(2) AND NOT adr(0) AND 
	adr(1) AND rgbSwt(5)));
db(5) <= db_I(5) when db_OE(5) = '1' else 'Z';
db_OE(5) <= (NOT cs AND NOT oe);FDCPE_regSsg13: FDCPE port map (regSsg(13),db(5).PIN,we,'0','0',regSsg_CE(13));
regSsg_CE(13) <= (NOT adr(5) AND NOT adr(4) AND NOT adr(3) AND NOT adr(2) AND NOT cs AND 
	adr(0) AND adr(1));


db(6) <= ((NOT N_PZ_229 AND rgbLcd(6).PIN)
	OR (regBtn(6) AND NOT adr(5) AND NOT adr(4) AND NOT adr(3) AND NOT adr(2) AND 
	NOT adr(0) AND NOT adr(1))
	OR (NOT adr(5) AND NOT adr(4) AND NOT adr(3) AND NOT adr(2) AND adr(0) AND 
	NOT adr(1) AND rgbBtnOt(4))
	OR (NOT adr(5) AND NOT adr(4) AND NOT adr(3) AND NOT adr(2) AND NOT adr(0) AND 
	adr(1) AND rgbSwt(6)));
db(6) <= db_I(6) when db_OE(6) = '1' else 'Z';
db_OE(6) <= (NOT cs AND NOT oe);FDCPE_regSsg14: FDCPE port map (regSsg(14),db(6).PIN,we,'0','0',regSsg_CE(14));
regSsg_CE(14) <= (NOT adr(5) AND NOT adr(4) AND NOT adr(3) AND NOT adr(2) AND NOT cs AND 
	adr(0) AND adr(1));


db(7) <= ((NOT N_PZ_229 AND rgbLcd(7).PIN)
	OR (regBtn(7) AND NOT adr(5) AND NOT adr(4) AND NOT adr(3) AND NOT adr(2) AND 
	NOT adr(0) AND NOT adr(1))
	OR (NOT adr(5) AND NOT adr(4) AND NOT adr(3) AND NOT adr(2) AND adr(0) AND 
	NOT adr(1) AND rgbBtnOt(5))
	OR (NOT adr(5) AND NOT adr(4) AND NOT adr(3) AND NOT adr(2) AND NOT adr(0) AND 
	adr(1) AND rgbSwt(7)));
db(7) <= db_I(7) when db_OE(7) = '1' else 'Z';
db_OE(7) <= (NOT cs AND NOT oe);FDCPE_regSsg15: FDCPE port map (regSsg(15),db(7).PIN,we,'0','0',regSsg_CE(15));
regSsg_CE(15) <= (NOT adr(5) AND NOT adr(4) AND NOT adr(3) AND NOT adr(2) AND NOT cs AND 
	adr(0) AND adr(1));


N_PZ_258 <= ((cntDig(0) AND cntDig(1) AND NOT regSsg(1) AND regSsg(2) AND 
	NOT regSsg(3))
	OR (cntDig(0) AND NOT cntDig(1) AND regSsg(10) AND NOT regSsg(11) AND 
	NOT regSsg(9))
	OR (NOT cntDig(0) AND cntDig(1) AND NOT regSsg(5) AND regSsg(6) AND 
	NOT regSsg(7))
	OR (NOT cntDig(0) AND NOT cntDig(1) AND NOT regSsg(13) AND regSsg(14) AND 
	NOT regSsg(15)));


db(1) <= ((NOT N_PZ_229 AND rgbLcd(1).PIN)
	OR (regBtn(1) AND NOT adr(5) AND NOT adr(4) AND NOT adr(3) AND NOT adr(2) AND 
	NOT adr(0) AND NOT adr(1))
	OR (regBtn(9) AND NOT adr(5) AND NOT adr(4) AND NOT adr(3) AND NOT adr(2) AND 
	adr(0) AND NOT adr(1))
	OR (NOT adr(5) AND NOT adr(4) AND NOT adr(3) AND NOT adr(2) AND NOT adr(0) AND 
	adr(1) AND rgbSwt(1)));
db(1) <= db_I(1) when db_OE(1) = '1' else 'Z';
db_OE(1) <= (NOT cs AND NOT oe);FDCPE_regSsg1: FDCPE port map (regSsg(1),db(1).PIN,we,'0','0',regSsg_CE(1));
regSsg_CE(1) <= (NOT adr(5) AND NOT adr(4) AND NOT adr(3) AND NOT adr(2) AND NOT cs AND 
	NOT adr(0) AND adr(1));

FDCPE_regSsg2: FDCPE port map (regSsg(2),db(2).PIN,we,'0','0',regSsg_CE(2));
regSsg_CE(2) <= (NOT adr(5) AND NOT adr(4) AND NOT adr(3) AND NOT adr(2) AND NOT cs AND 
	NOT adr(0) AND adr(1));

FDCPE_regSsg3: FDCPE port map (regSsg(3),db(3).PIN,we,'0','0',regSsg_CE(3));
regSsg_CE(3) <= (NOT adr(5) AND NOT adr(4) AND NOT adr(3) AND NOT adr(2) AND NOT cs AND 
	NOT adr(0) AND adr(1));

FDCPE_regSsg5: FDCPE port map (regSsg(5),db(5).PIN,we,'0','0',regSsg_CE(5));
regSsg_CE(5) <= (NOT adr(5) AND NOT adr(4) AND NOT adr(3) AND NOT adr(2) AND NOT cs AND 
	NOT adr(0) AND adr(1));

FDCPE_regSsg6: FDCPE port map (regSsg(6),db(6).PIN,we,'0','0',regSsg_CE(6));
regSsg_CE(6) <= (NOT adr(5) AND NOT adr(4) AND NOT adr(3) AND NOT adr(2) AND NOT cs AND 
	NOT adr(0) AND adr(1));

FDCPE_regSsg7: FDCPE port map (regSsg(7),db(7).PIN,we,'0','0',regSsg_CE(7));
regSsg_CE(7) <= (NOT adr(5) AND NOT adr(4) AND NOT adr(3) AND NOT adr(2) AND NOT cs AND 
	NOT adr(0) AND adr(1));


N_PZ_230 <= ((cntDig(0) AND NOT regSsg(1) AND regSsg(2) AND regSsg(3))
	OR (NOT cntDig(0) AND NOT regSsg(5) AND regSsg(6) AND regSsg(7)));


N_PZ_232 <= ((cntDig(0) AND NOT regSsg(1) AND NOT regSsg(2) AND NOT regSsg(3))
	OR (NOT cntDig(0) AND NOT regSsg(5) AND NOT regSsg(6) AND NOT regSsg(7)));


N_PZ_302 <= ((cntDig(0) AND regSsg(1) AND NOT regSsg(2) AND regSsg(3))
	OR (NOT cntDig(0) AND regSsg(5) AND NOT regSsg(6) AND regSsg(7)));


rgbSsgCa(1) <= ((dig(0) AND N_PZ_258)
	OR (NOT dig(0) AND N_PZ_264)
	OR (cntDig(0) AND NOT cntDig(1) AND NOT dig(0) AND N_PZ_335)
	OR (NOT cntDig(0) AND cntDig(1) AND NOT dig(0) AND N_PZ_283)
	OR (cntDig(0) AND cntDig(1) AND dig(0) AND regSsg(1) AND 
	regSsg(3))
	OR (cntDig(0) AND cntDig(1) AND NOT dig(0) AND regSsg(1) AND 
	regSsg(2))
	OR (cntDig(0) AND NOT cntDig(1) AND dig(0) AND regSsg(11) AND 
	regSsg(9))
	OR (NOT cntDig(0) AND cntDig(1) AND dig(0) AND regSsg(5) AND 
	regSsg(7))
	OR (NOT cntDig(0) AND NOT cntDig(1) AND dig(0) AND regSsg(13) AND 
	regSsg(15))
	OR (NOT cntDig(0) AND NOT cntDig(1) AND NOT dig(0) AND regSsg(13) AND 
	regSsg(14)));


N_PZ_264 <= ((cntDig(0) AND cntDig(1) AND regSsg(2) AND regSsg(3))
	OR (cntDig(0) AND NOT cntDig(1) AND regSsg(10) AND regSsg(11))
	OR (NOT cntDig(0) AND cntDig(1) AND regSsg(6) AND regSsg(7))
	OR (NOT cntDig(0) AND NOT cntDig(1) AND regSsg(14) AND regSsg(15)));


N_PZ_283 <= (regSsg(5) AND regSsg(6));


N_PZ_335 <= (regSsg(10) AND regSsg(9));


rgbSsgCa(2) <= ((NOT dig(0) AND N_PZ_264)
	OR (NOT dig(0) AND N_PZ_267)
	OR (cntDig(0) AND NOT cntDig(1) AND regSsg(11) AND N_PZ_335)
	OR (NOT cntDig(0) AND cntDig(1) AND regSsg(7) AND N_PZ_283)
	OR (cntDig(0) AND cntDig(1) AND regSsg(1) AND regSsg(2) AND 
	regSsg(3))
	OR (NOT cntDig(0) AND NOT cntDig(1) AND regSsg(13) AND regSsg(14) AND 
	regSsg(15)));


N_PZ_267 <= ((cntDig(0) AND cntDig(1) AND regSsg(1) AND NOT regSsg(2) AND 
	NOT regSsg(3))
	OR (cntDig(0) AND NOT cntDig(1) AND NOT regSsg(10) AND NOT regSsg(11) AND 
	regSsg(9))
	OR (NOT cntDig(0) AND cntDig(1) AND regSsg(5) AND NOT regSsg(6) AND 
	NOT regSsg(7))
	OR (NOT cntDig(0) AND NOT cntDig(1) AND regSsg(13) AND NOT regSsg(14) AND 
	NOT regSsg(15)));


rgbSsgCa(3) <= ((NOT dig(0) AND N_PZ_258)
	OR (cntDig(1) AND dig(0) AND N_PZ_232)
	OR (cntDig(1) AND NOT dig(0) AND N_PZ_302)
	OR (NOT cntDig(1) AND dig(0) AND regBtn(5).COMB)
	OR (cntDig(0) AND NOT cntDig(1) AND dig(0) AND N_PZ_335)
	OR (NOT cntDig(0) AND cntDig(1) AND dig(0) AND N_PZ_283)
	OR (cntDig(0) AND cntDig(1) AND dig(0) AND regSsg(1) AND 
	regSsg(2))
	OR (NOT cntDig(0) AND NOT cntDig(1) AND dig(0) AND regSsg(13) AND 
	regSsg(14))
	OR (cntDig(0) AND NOT cntDig(1) AND NOT dig(0) AND NOT regSsg(10) AND 
	regSsg(11) AND regSsg(9))
	OR (NOT cntDig(0) AND NOT cntDig(1) AND NOT dig(0) AND regSsg(13) AND 
	NOT regSsg(14) AND regSsg(15)));


rgbSsgCa(4) <= ((N_PZ_258)
	OR (cntDig(0) AND cntDig(1) AND dig(0) AND NOT regSsg(3))
	OR (cntDig(0) AND NOT cntDig(1) AND dig(0) AND NOT regSsg(11))
	OR (NOT cntDig(0) AND cntDig(1) AND dig(0) AND NOT regSsg(7))
	OR (NOT cntDig(0) AND NOT cntDig(1) AND dig(0) AND NOT regSsg(15))
	OR (cntDig(0) AND cntDig(1) AND dig(0) AND NOT regSsg(1) AND 
	NOT regSsg(2))
	OR (cntDig(0) AND NOT cntDig(1) AND dig(0) AND NOT regSsg(10) AND 
	NOT regSsg(9))
	OR (NOT cntDig(0) AND cntDig(1) AND dig(0) AND NOT regSsg(5) AND 
	NOT regSsg(6))
	OR (NOT cntDig(0) AND NOT cntDig(1) AND dig(0) AND NOT regSsg(13) AND 
	NOT regSsg(14)));


rgbSsgCa(5) <= NOT (((NOT dig(0) AND NOT N_PZ_267)
	OR (cntDig(0) AND cntDig(1) AND regSsg(3) AND NOT N_PZ_230 AND 
	NOT N_PZ_267)
	OR (NOT cntDig(0) AND cntDig(1) AND regSsg(7) AND NOT N_PZ_230 AND 
	NOT N_PZ_267)
	OR (cntDig(0) AND cntDig(1) AND NOT regSsg(1) AND regSsg(2) AND 
	NOT N_PZ_230 AND NOT N_PZ_267)
	OR (cntDig(0) AND NOT cntDig(1) AND regSsg(11) AND 
	NOT regBtn(4).COMB AND NOT regBtn(5).COMB AND NOT N_PZ_267)
	OR (cntDig(0) AND NOT cntDig(1) AND NOT regSsg(9) AND 
	NOT regBtn(4).COMB AND NOT regBtn(5).COMB AND NOT N_PZ_267)
	OR (NOT cntDig(0) AND cntDig(1) AND regSsg(6) AND NOT N_PZ_230 AND 
	NOT N_PZ_283 AND NOT N_PZ_267)
	OR (NOT cntDig(0) AND NOT cntDig(1) AND NOT regSsg(13) AND 
	NOT regBtn(4).COMB AND NOT regBtn(5).COMB AND NOT N_PZ_267)
	OR (NOT cntDig(0) AND NOT cntDig(1) AND regSsg(15) AND 
	NOT regBtn(4).COMB AND NOT regBtn(5).COMB AND NOT N_PZ_267)));


rgbSsgCa(6) <= ((cntDig(1) AND N_PZ_232)
	OR (NOT cntDig(1) AND regBtn(5).COMB)
	OR (cntDig(1) AND NOT dig(0) AND N_PZ_230)
	OR (NOT cntDig(1) AND NOT dig(0) AND regBtn(4).COMB)
	OR (cntDig(0) AND NOT cntDig(1) AND dig(0) AND NOT regSsg(11) AND 
	N_PZ_335)
	OR (NOT cntDig(0) AND cntDig(1) AND dig(0) AND NOT regSsg(7) AND 
	N_PZ_283)
	OR (cntDig(0) AND cntDig(1) AND dig(0) AND regSsg(1) AND 
	regSsg(2) AND NOT regSsg(3))
	OR (NOT cntDig(0) AND NOT cntDig(1) AND dig(0) AND regSsg(13) AND 
	regSsg(14) AND NOT regSsg(15)));


rgbSsgCa(7) <= '1';


N_PZ_229 <= ((NOT adr(5) AND NOT adr(4) AND NOT adr(3) AND NOT adr(2) AND NOT adr(0))
	OR (NOT adr(5) AND NOT adr(4) AND NOT adr(3) AND NOT adr(2) AND NOT adr(1)));


Register Legend:
 FDCPE (Q,D,C,CLR,PRE,CE); 
 FTCPE (Q,D,C,CLR,PRE,CE); 
 LDCP  (Q,D,G,CLR,PRE); 

****************************  Device Pin Out ****************************

Device : XCR3128XL-7-TQ144


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 lcdrw                            73 VCC                           
  2 lcdrs                            74 adr<0>                        
  3 GND                              75 NC                            
  4 TDI                              76 VCC                           
  5 WPU                              77 db<0>                         
  6 WPU                              78 adr<1>                        
  7 kdin                             79 db<1>                         
  8 kcin                             80 adr<2>                        
  9 rgbSsgAn<0>                      81 db<2>                         
 10 rgbSsgAn<1>                      82 adr<3>                        
 11 rgbSsgAn<2>                      83 db<3>                         
 12 rgbSsgAn<3>                      84 adr<4>                        
 13 PE                               85 GND                           
 14 rgbSsgCa<7>                      86 db<4>                         
 15 rgbSsgCa<6>                      87 adr<5>                        
 16 rgbSsgCa<5>                      88 db<5>                         
 17 GND                              89 TCK                           
 18 rgbSsgCa<4>                      90 db<6>                         
 19 NC                               91 oe                            
 20 TMS                              92 db<7>                         
 21 rgbSsgCa<3>                      93 cs                            
 22 rgbSsgCa<2>                      94 rgbSwt<7>                     
 23 rgbSsgCa<1>                      95 VCC                           
 24 VCC                              96 rgbSwt<6>                     
 25 rgbSsgCa<0>                      97 rgbSwt<5>                     
 26 rgbLed<15>                       98 rgbSwt<4>                     
 27 rgbLed<14>                       99 rgbSwt<3>                     
 28 rgbLed<13>                      100 rgbSwt<2>                     
 29 rgbLed<12>                      101 rgbSwt<1>                     
 30 rgbLed<11>                      102 rgbSwt<0>                     
 31 rgbLed<10>                      103 NC                            
 32 rgbLed<9>                       104 TDO                           
 33 GND                             105 GND                           
 34 NC                              106 WPU                           
 35 NC                              107 lcen                          
 36 NC                              108 NC                            
 37 rgbLed<8>                       109 encBtn<0>                     
 38 rgbLed<7>                       110 encBtn<1>                     
 39 rgbLed<6>                       111 encBtn<2>                     
 40 rgbLed<5>                       112 encBtn<3>                     
 41 rgbLed<4>                       113 rgbBtnOt<0>                   
 42 rgbLed<3>                       114 rgbBtnOt<1>                   
 43 NC                              115 VCC                           
 44 rgbLed<2>                       116 rgbBtnOt<2>                   
 45 rgbLed<1>                       117 rgbBtnOt<3>                   
 46 rgbLed<0>                       118 rgbBtnOt<4>                   
 47 NC                              119 rgbBtnOt<5>                   
 48 NC                              120 kclk                          
 49 NC                              121 kdat                          
 50 VCC                             122 NC                            
 51 VCC                             123 VCC                           
 52 GND                             124 GND                           
 53 rgbBtnIn<7>                     125 we                            
 54 rgbBtnIn<8>                     126 TIE                           
 55 rgbBtnIn<9>                     127 clk                           
 56 rgbBtnIn<12>                    128 TIE                           
 57 GND                             129 GND                           
 58 VCC                             130 VCC                           
 59 GND                             131 WPU                           
 60 rgbBtnIn<4>                     132 WPU                           
 61 rgbBtnIn<5>                     133 WPU                           
 62 rgbBtnIn<6>                     134 rgbLcd<0>                     
 63 rgbBtnIn<13>                    135 GND                           
 64 GND                             136 rgbLcd<1>                     
 65 rgbBtnIn<1>                     137 rgbLcd<2>                     
 66 rgbBtnIn<2>                     138 rgbLcd<3>                     
 67 rgbBtnIn<3>                     139 rgbLcd<4>                     
 68 rgbBtnIn<14>                    140 rgbLcd<5>                     
 69 rgbBtnIn<0>                     141 rgbLcd<6>                     
 70 rgbBtnIn<10>                    142 rgbLcd<7>                     
 71 rgbBtnIn<11>                    143 lcden                         
 72 rgbBtnIn<15>                    144 VCC                           


Legend :  NC  = Not Connected, unbonded pin
          PE  = Port Enable pin
         WPU  = Unused with Internal Weak Pull Up
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xcr3128xl-7-TQ144
Optimization Method                         : DENSITY
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : ON
Keep Unused Inputs                          : OFF
Slew Rate                                   : SLOW
Set Unused I/O Pin Termination              : PULLUP
Set Input-Only Termination                  : FLOAT
Set Universal Control Term Optimization     : OFF
Enable Foldback NANDs                       : ON
Reserve ISP Pins                            : ON
Enable Input Registers                      : ON
Function Block Fan-in Limit                 : 39
Input Limit                                 : 17
Pterm Limit                                 : 28