kamera Project Status (03/25/2010 - 13:54:33)
Project File: kamera.ise Implementation State: Programming File Generated
Module Name: Kamera
  • Errors:
No Errors
Target Device: xc3s1000-5ft256
  • Warnings:
656 Warnings
Product Version:ISE 11.3
  • Routing Results:
All Signals Completely Routed
Design Goal: Balanced
  • Timing Constraints:
X 3 Failing Constraints
Design Strategy: Xilinx Default (unlocked)
  • Final Timing Score:
106617 (Setup: 106617, Hold: 0, Component Switching Limit: 0) (Timing Report)
 
kamera Partition Summary [-]
No partition information was found.
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 552 15,360 3%  
Number of 4 input LUTs 836 15,360 5%  
Number of occupied Slices 599 7,680 7%  
    Number of Slices containing only related logic 599 599 100%  
    Number of Slices containing unrelated logic 0 599 0%  
Total Number of 4 input LUTs 1,005 15,360 6%  
    Number used as logic 836      
    Number used as a route-thru 169      
Number of bonded IOBs 164 173 94%  
    IOB Flip Flops 157      
Number of MULT18X18s 1 24 4%  
Number of BUFGMUXs 4 8 50%  
Number of DCMs 1 4 25%  
Average Fanout of Non-Clock Nets 3.08      
 
Performance Summary [-]
Final Timing Score: 106617 (Setup: 106617, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: X 3 Failing Constraints    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentDo 25. Mrz 13:50:08 2010068 Warnings18 Infos
Translation ReportCurrentDo 25. Mrz 13:51:05 2010000
Map ReportCurrentDo 25. Mrz 13:51:30 20100564 Warnings3 Infos
Place and Route ReportCurrentDo 25. Mrz 13:53:56 2010014 Warnings3 Infos
Post-PAR Static Timing ReportCurrentDo 25. Mrz 13:54:06 2010003 Infos
Bitgen ReportCurrentDo 25. Mrz 13:54:25 2010010 Warnings1 Info
 
Secondary Reports [-]
Report NameStatusGenerated

Date Generated: 03/25/2010 - 13:54:33