t89c51cc02.h

00001 /*****************************************************************************
00002 * NAME:           t89c51cc02.h
00003 *------------------------------------------------------------------------------
00004 * PURPOSE:
00005 *   This file defines Sfr registers and BIT Registers for T89C51CC02
00006 *               ON SDCC compiler
00007 ******************************************************************************/
00008 #ifndef _T89C51CC02_H_
00009 
00010 #define _T89C51CC02_H_
00011 
00012 /* PATCH for SDCC by Matthias Arndt <matthias.arndt@tu-clausthal.de>*/
00013 
00014 #define Sfr(x, y)               __sfr __at (y) x
00015 #define Sbit(x, y, z)           __sbit __at (y^z) x
00016 
00017 /*----------------------------------------*/
00018 /* Include file for 8051 SFR Definitions  */
00019 /*----------------------------------------*/
00020 
00021 /*  BYTE Register  */
00022 Sfr (P1 , 0x90);        
00023 
00024 Sbit (P1_7, 0x90, 7);
00025 Sbit (P1_6, 0x90, 6);
00026 Sbit (P1_5, 0x90, 5);
00027 Sbit (P1_4, 0x90, 4);
00028 Sbit (P1_3, 0x90, 3);
00029 Sbit (P1_2, 0x90, 2);
00030 Sbit (P1_1, 0x90, 1);
00031 Sbit (P1_0, 0x90, 0);
00032 
00033 Sfr (P2 , 0xA0);        
00034 
00035 Sbit (P2_1 , 0xA0, 1);
00036 Sbit (P2_0 , 0xA0, 0);
00037 
00038 
00039 Sfr (P3 , 0xB0);        
00040 
00041 Sbit (P3_7 , 0xB0, 7);
00042 Sbit (P3_6 , 0xB0, 6);
00043 Sbit (P3_5 , 0xB0, 5);
00044 Sbit (P3_4 , 0xB0, 4);
00045 Sbit (P3_3 , 0xB0, 3);
00046 Sbit (P3_2 , 0xB0, 2);
00047 Sbit (P3_1 , 0xB0, 1);
00048 Sbit (P3_0 , 0xB0, 0);
00049 
00050 Sbit (RD , 0xB0, 7);
00051 Sbit (WR , 0xB0, 6);
00052 Sbit (T1 , 0xB0, 5);
00053 Sbit (T0 , 0xB0, 4);
00054 Sbit (INT1, 0xB0, 3);
00055 Sbit (INT0, 0xB0, 2);
00056 Sbit (TXD , 0xB0, 1);
00057 Sbit (RXD , 0xB0, 0);
00058 
00059 Sfr (P4 , 0xC0);        
00060 
00061 Sfr (PSW , 0xD0);       
00062 
00063 Sbit (CY  , 0xD0, 7);
00064 Sbit (AC  , 0xD0, 6);
00065 Sbit (F0  , 0xD0, 5);
00066 Sbit (RS1 , 0xD0, 4);
00067 Sbit (RS0 , 0xD0, 3);
00068 Sbit (OV  , 0xD0, 2);
00069 Sbit (UD  , 0xD0, 1);
00070 Sbit (P   , 0xD0, 0);
00071 
00072 Sfr (ACC , 0xE0);       
00073 Sfr (B , 0xF0); 
00074 Sfr (SP , 0x81);        
00075 Sfr (DPL , 0x82);       
00076 Sfr (DPH , 0x83);       
00077 
00078 Sfr (PCON , 0x87);      
00079 Sfr (CKCON , 0x8F);     
00080 
00081 /*------------------ TIMERS registers ---------------------*/
00082 Sfr (TCON , 0x88);
00083 Sbit (TF1 , 0x88, 7);
00084 Sbit (TR1 , 0x88, 6);
00085 Sbit (TF0 , 0x88, 5);
00086 Sbit (TR0 , 0x88, 4);
00087 Sbit (IE1 , 0x88, 3);
00088 Sbit (IT1 , 0x88, 2);
00089 Sbit (IE0 , 0x88, 1);
00090 Sbit (IT0 , 0x88, 0);
00091         
00092 Sfr (TMOD , 0x89);      
00093 
00094 Sfr  (T2CON , 0xC8);
00095 Sbit (TF2   , 0xC8, 7);
00096 Sbit (EXF2  , 0xC8, 6);
00097 Sbit (RCLK  , 0xC8, 5);
00098 Sbit (TCLK  , 0xC8, 4);
00099 Sbit (EXEN2 , 0xC8, 3);
00100 Sbit (TR2   , 0xC8, 2);
00101 Sbit (C_T2  , 0xC8, 1);
00102 Sbit (CP_RL2, 0xC8, 0);
00103         
00104 Sfr (T2MOD , 0xC9);     
00105 Sfr (TL0 , 0x8A);       
00106 Sfr (TL1 , 0x8B);       
00107 Sfr (TL2 , 0xCC);       
00108 Sfr (TH0 , 0x8C);       
00109 Sfr (TH1 , 0x8D);       
00110 Sfr (TH2 , 0xCD);       
00111 Sfr (RCAP2L , 0xCA);    
00112 Sfr (RCAP2H , 0xCB);    
00113 Sfr (WDTRST , 0xA6);    
00114 Sfr (WDTPRG , 0xA7);    
00115 
00116 
00117 /*------------------- UART registers ------------------------*/
00118 Sfr (SCON , 0x98);      
00119 Sbit (SM0  , 0x98, 7);
00120 Sbit (FE   , 0x98, 7);
00121 Sbit (SM1  , 0x98, 6);
00122 Sbit (SM2  , 0x98, 5);
00123 Sbit (REN  , 0x98, 4);
00124 Sbit (TB8  , 0x98, 3);
00125 Sbit (RB8  , 0x98, 2);
00126 Sbit (TI   , 0x98, 1);
00127 Sbit (RI   , 0x98, 0);
00128 
00129 Sfr (SBUF , 0x99);      
00130 Sfr (SADEN , 0xB9);     
00131 Sfr (SADDR , 0xA9);     
00132 
00133 /*-------------------- ADC registers ----------------------*/
00134 Sfr (ADCLK , 0xF2);     
00135 Sfr (ADCON , 0xF3);     
00136 #define MSK_ADCON_PSIDLE 0x40
00137 #define MSK_ADCON_ADEN   0x20
00138 #define MSK_ADCON_ADEOC  0x10
00139 #define MSK_ADCON_ADSST  0x08
00140 #define MSK_ADCON_SCH    0x07
00141 Sfr (ADDL , 0xF4);      
00142 #define MSK_ADDL_UTILS   0x03
00143 Sfr (ADDH , 0xF5);      
00144 Sfr (ADCF , 0xF6);      
00145 
00146 /*-------------------- FLASH EEPROM registers ------------*/
00147 Sfr (FCON  , 0xD1);     
00148 #define MSK_FCON_FBUSY 0x01
00149 #define MSK_FCON_FMOD  0x06
00150 #define MSK_FCON_FPS   0x08
00151 #define MSK_FCON_FPL   0xF0
00152 Sfr (EECON  , 0xD2);    
00153 #define MSK_EECON_EEBUSY 0x01
00154 #define MSK_EECON_EEE    0x02
00155 #define MSK_EECON_EEPL   0xF0
00156 Sfr (AUXR  , 0x8E);     
00157 #define MSK_AUXR_M0      0x20
00158 Sfr (AUXR1  , 0xA2);    
00159 #define MSK_AUXR1_ENBOOT 0x20
00160 /*-------------------- IT registers -----------------------*/
00161 Sfr (IPL1 , 0xF8);      
00162 Sfr (IPH1 , 0xF7);      
00163 Sfr (IEN0  , 0xA8);     
00164 Sfr (IPL0 , 0xB8);      
00165 Sfr (IPH0 , 0xB7);      
00166 Sfr (IEN1  , 0xE8);     
00167 
00168 /*  IEN0  */
00169 Sbit (EA   , 0xA8, 7);
00170 Sbit (EC   , 0xA8, 6);
00171 Sbit (ET2  , 0xA8, 5);
00172 Sbit (ES   , 0xA8, 4);
00173 Sbit (ET1  , 0xA8, 3);
00174 Sbit (EX1  , 0xA8, 2);
00175 Sbit (ET0  , 0xA8, 1);
00176 Sbit (EX0  , 0xA8, 0);
00177 
00178 /*  IEN1  */
00179 Sbit (ETIM , 0xE8, 2);
00180 Sbit (EADC , 0xE8, 1);
00181 Sbit (ECAN , 0xE8, 0);
00182 
00183 /*--------------------- PCA registers --------------------*/
00184 Sfr (CCON , 0xD8);      
00185 Sbit(CF  , 0xD8, 7);
00186 Sbit(CR  , 0xD8, 6);
00187 Sbit(CCF4, 0xD8, 4);
00188 Sbit(CCF3, 0xD8, 3);
00189 Sbit(CCF2, 0xD8, 2);
00190 Sbit(CCF1, 0xD8, 1);
00191 Sbit(CCF0, 0xD8, 0);
00192 
00193 Sfr (CMOD , 0xD9);      
00194 Sfr (CH , 0xF9);        
00195 Sfr (CL , 0xE9);        
00196 Sfr (CCAP0H  , 0xFA);   
00197 Sfr (CCAP0L  , 0xEA);   
00198 Sfr (CCAPM0  , 0xDA);   
00199 Sfr (CCAP1H  , 0xFB);   
00200 Sfr (CCAP1L  , 0xEB);   
00201 Sfr (CCAPM1  , 0xDB);   
00202 Sfr (CCAP2H  , 0xFC);   
00203 Sfr (CCAP2L  , 0xEC);   
00204 Sfr (CCAPM2  , 0xDC);   
00205 Sfr (CCAP3H  , 0xFD);   
00206 Sfr (CCAP3L  , 0xED);   
00207 Sfr (CCAPM3  , 0xDD);   
00208 Sfr (CCAP4H  , 0xFE);   
00209 Sfr (CCAP4L  , 0xEE);   
00210 Sfr (CCAPM4  , 0xDE);   
00211 
00212 /*------------------- CAN registers --------------------------*/
00213 Sfr (CANGIT , 0x9B);
00214 #define MSK_CANGIT_CANIT        0x80
00215 #define MSK_CANGIT_OVRTIM       0x20
00216 #define MSK_CANGIT_OVRBUF       0x10    
00217 #define MSK_CANGIT_SERG         0x08
00218 #define MSK_CANGIT_CERG         0x04
00219 #define MSK_CANGIT_FERG         0x02
00220 #define MSK_CANGIT_AERG         0x01
00221 
00222 Sfr (CANTEC , 0x9C);    
00223 Sfr (CANREC , 0x9D);    
00224 Sfr (CANTCON , 0xA1);   
00225 Sfr (CANMSG , 0xA3);    
00226 Sfr (CANTTCL , 0xA4);   
00227 Sfr (CANTTCH , 0xA5);   
00228 Sfr (CANGSTA , 0xAA);   
00229 #define MSK_CANGSTA_OVFG        0x40
00230 #define MSK_CANGSTA_TBSY        0x10
00231 #define MSK_CANGSTA_RBSY        0x08
00232 #define MSK_CANGSTA_ENFG        0x04
00233 #define MSK_CANGSTA_BOFF        0x02
00234 #define MSK_CANGSTA_ERRP        0x01
00235 
00236 Sfr (CANGCON , 0xAB);   
00237 #define MSK_CANGCON_ABRQ        0x80
00238 #define MSK_CANGCON_OVRQ        0x40
00239 #define MSK_CANGCON_TTC         0x20
00240 #define MSK_CANGCON_SYNCTTC     0x10
00241 #define TTC_EOF                 0x10
00242 #define TTC_SOF                 0x00
00243 #define MSK_CANGCON_AUTBAUD     0x08
00244 #define MSK_CANGCON_ENA         0x02
00245 #define MSK_CANGCON_GRES        0x01
00246 
00247 
00248 Sfr (CANTIML , 0xAC);   
00249 Sfr (CANTIMH , 0xAD);   
00250 Sfr (CANSTMPL , 0xAE);  
00251 Sfr (CANSTMPH , 0xAF);  
00252 Sfr (CANPAGE , 0xB1);   
00253 Sfr (CANSTCH , 0xB2);   
00254 #define MSK_CANSTCH_DLCW  0x80
00255 #define MSK_CANSTCH_TxOk  0x40
00256 #define MSK_CANSTCH_RxOk  0x20
00257 #define MSK_CANSTCH_BERR  0x10
00258 #define MSK_CANSTCH_SERR  0x08
00259 #define MSK_CANSTCH_CERR  0x04
00260 #define MSK_CANSTCH_FERR  0x02
00261 #define MSK_CANSTCH_AERR  0x01
00262 
00263 Sfr (CANCONCH , 0xB3);  
00264 #define MSK_CANCONCH_IDE  0x10
00265 #define MSK_CANCONCH_DLC  0x0F
00266 #define MSK_CANCONCH_CONF 0xC0
00267 #define DLC_MAX    8
00268 #define CH_DISABLE 0x00
00269 #define CH_RxENA   0x80
00270 #define CH_TxENA   0x40
00271 #define CH_RxBENA  0xC0
00272 
00273 Sfr (CANBT1 , 0xB4);
00274 #define CAN_PRESCALER_MIN  0
00275 #define CAN_PRESCALER_MAX  63
00276         
00277 Sfr (CANBT2 , 0xB5);
00278 #define MSK_CANBT2_SJW  0x60
00279 #define MSK_CANBT2_PRS  0x0E
00280 #define CAN_SJW_MIN  0
00281 #define CAN_SJW_MAX  3
00282 #define CAN_PRS_MIN  0
00283 #define CAN_PRS_MAX  7
00284         
00285 Sfr (CANBT3 , 0xB6);
00286 #define MSK_CANBT3_PHS2 0x70
00287 #define MSK_CANBT3_PHS1 0x0E
00288 #define CAN_PHS2_MIN 0
00289 #define CAN_PHS2_MAX 7
00290 #define CAN_PHS1_MIN 0
00291 #define CAN_PHS1_MAX 7
00292         
00293 Sfr (CANSIT , 0xBB);    
00294 Sfr (CANIDT1 , 0xBC);   
00295 Sfr (CANIDT2 , 0xBD);   
00296 Sfr (CANIDT3 , 0xBE);   
00297 Sfr (CANIDT4 , 0xBF);   
00298 #define MSK_CANIDT4_RTRTAG 0x04
00299 
00300 Sfr (CANGIE , 0xC1);    
00301 #define MSK_CANGIE_ENRX    0x20
00302 #define MSK_CANGIE_ENTX    0x10
00303 #define MSK_CANGIE_ENERCH  0x08
00304 #define MSK_CANGIE_ENBUF   0x04
00305 #define MSK_CANGIE_ENERG   0x02
00306 
00307 Sfr (CANIE , 0xC3);     
00308 Sfr (CANIDM1 , 0xC4);   
00309 Sfr (CANIDM2 , 0xC5);   
00310 Sfr (CANIDM3 , 0xC6);   
00311 Sfr (CANIDM4 , 0xC7);
00312 #define MSK_CANIDM4_RTRMSK 0x04
00313 #define MSK_CANIDM4_IDEMSK 0x01 
00314         
00315 Sfr (CANEN , 0xCF);     
00316 
00317 #endif
00318 

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