Project Statistics |
PROP_Synthesis_Tool=XST (VHDL/Verilog) |
PROP_Simulator=ISim (VHDL/Verilog) |
PROP_Top_Level_Module_Type=HDL |
PROP_PreferredLanguage=VHDL |
PROP_Enable_Message_Filtering=false |
PROP_Enable_Incremental_Messaging=false |
PROP_UseSmartGuide=false |
Partitions count=1 |
FILE_COREGEN=1 |
FILE_UCF=1 |
FILE_VHDL=10 |
PROP_CompxlibOverwriteLib=true |
PROP_DevDevice=xc3s1000 |
PROP_DevFamily=Spartan3 |
PROP_DevPackage=ft256 |
PROP_FitterReportFormat=HTML |
PROP_MapExtraEffort=Normal |
PROP_MapLogicOptimization=true |
PROP_PostTrceFastPath=false |
PROP_PreTrceFastPath=false |
PROP_PreferredLanguage=VHDL |
PROP_Simulator=ISim (VHDL/Verilog) |
PROP_SynthConstraintsFile=changed |
PROP_SynthOptEffort=High |
PROP_UserConstraintEditorPreference=Constraints Editor |
PROP_intWorkingDirLocWRTProjDir=Same |
PROP_intWorkingDirUsed=No |
PROP_xilxBitgStart_Clk=JTAG Clock |
PROP_xilxMapPackRegInto=For Inputs and Outputs |
PROP_xilxPARextraEffortLevel=Normal |
PROP_xilxPARplacerEffortLevel=High |
PROP_xilxPARrouterEffortLevel=High |
PROP_xilxSynthRegBalancing=Yes |
PROP_xstNetlistHierarchy=Rebuilt |
PROP_xstOptimizeInsPrimtives=true |
PROP_xstPackIORegister=Yes |
PROP_xstWriteTimingConstraints=true |
Project duration(days)= |